Scan testing is a well established technique for checking the functionality of logic circuits. A brief explanation of scan testing follows by way of background to the invention.
FIG. 1 illustrates schematically the structure of part of a functional logic circuit. The functional logic circuit can be considered to consist of blocks of combinational logic 2a, 2b connected to clocked memory elements or latches 4a, 4b, 4c. The combinational logic blocks represent purely combinational logic, that is where the output depends only on an extant set of inputs with no clocked circuits. The latch 4a receives as its data input an output on line 7a from the combinational logic block 2a, and generates its output on line 6a. The latch 4b receives as its data input another input on line 7b from the combinational logic block 2a, and generates its output on line 6b. The latch 4c receives as its data input an output on line 7c from the combinational logic block 2b, and generates its output on line 6c. The combinational logic block 2a receives a plurality of data inputs 5a to 5e. The data input 5a is taken from the output line 6a and the data input 5e is taken from the output line 6b. The combinational logic block 2b receives a plurality of inputs 5f, 5g, 5h and 5e. It will be understood that the structure of FIG. 1 is given only by means of an illustrative example and the combinational logic blocks 2a and 2b may in practice have a much larger number of inputs. It will also be understood that in the example of FIG. 1 additional combinational logic blocks and latches do in practice exist. The latches 4a, 4b and 4c are clocked by a common clock signal CLOCK connected to the respective latches by means of a common clock signal line 8.
It is desirable to test the structure of the combinational logic blocks placed between memory elements to ensure they function correctly. To do this it is necessary to put known test bits on the inputs of the combinational logic blocks and then check that the results generated at the outputs of the combinational logic blocks are those expected for the given test bits on the inputs. This is achieved by replacing each of the latches 4a, 4b and 4c in the functional logic circuitry of FIG. 1 with a respective scan cell 10a, 10b and 10c as is shown in FIG. 2. In FIG. 2, like reference numerals have been used for components and connections which are common to FIG. 1.
Referring to FIG. 2, each of the scan cells 10a, 10b and 10c comprises a multiplexor 12a, 12b and 12c and a latch 16a, 16b and 16c. The latches 16a, 16b and 16c may be the same as the latches 4a, 4b and 4c of FIG. 1. The multiplexor 12a has an input DATAIN on line 18a connected to the output generated by the combinational logic block 2a on line 7a, and an input SCANIN on line 20a connected to an output of a control circuit 11 on line 3. The multiplexor 12b has an input on line 18b connected to the output generated by the combinational logic block 2a on line 7b, and an input on line 20b connected to the output line 6a. The multiplexor 12c has an input on line 18c connected to the output generated by the combinational logic block 2b, and an input on line 20c connected to the output line 6b. The outputs of the multiplexors 12a, 12b and 12c are respectively connected to the latches 16a, 16b and 16c via the signal lines 24a, 24b and 24c. The output CELLOUT of the latch 16a on line 22a is connected to the output signal line 6a, the output of the latch 16b on line 22b is connected to the output signal line 6b, and the output of latch 16c on line 22c is connected to the output signal line 6c, which in turn is connected to the control circuit 11 via line 9. The latches 16a, 16b and 16c are clocked by the common clock signal CLOCK on line 8, and the multiplexors 12a, 12b and 12c are controlled by a common control signal CONTROL1 on line 14.
The multiplexors 12a, 12b and 12c are provided for the purpose of performing scan testing. In normal functional operation the multiplexors 12a, 12b and 12c operate to provide direct connection between the signals on the input lines 18a, 18b and 18c and the signals on the output lines 24a, 24b and 24c respectively. This configuration of the multiplexors 12a, 12b and 12c is set by controlling the signal CONTROL1 on line 14. Consequently during normal functional operation the structure of FIG. 2 is configured as the structure of FIG. 1.
When a scan test is to be performed, the signal CONTROL1 on line 14 will be set such that the multiplexors 12a, 12b and 12c connect their respective inputs on lines 20a, 20b and 20c to their respective outputs on lines 24a, 24b and 24c. Thus it can be seen that the multiplexors 12a, 12b, 12c and latches 16a, 16b and 16c form a serial scan chain. In order to carry out the scan test it is necessary to place a known test bit on each of the respective input signal lines 5a to 5g of the combinational logic blocks 2a, 2b. With the multiplexors 12a, 12b and 12c configured to connect their inputs 20a, 20b and 20c to their outputs 24a, 24b and 24c a sequence of test bits is outputted serially on line 3 by the control circuit 11 under the control of the clock signal CLOCK, such that the test bits are serially clocked through the latches 16a, 16b and 16c in sequence. After a plurality of clock cycles equal to the number of scan cells in the scan chain, each of the signal lines 6a, 6b, 6c will have a known test bit thereon stored by means of the latches 16a, 16b and 16c. The outputs of the combinational logic blocks 2a, 2b will then change according to the new input values set, and these new output values will appear on the inputs 18a, 18b and 18c of the multiplexors 12a, 12b and 12c. It will be understood, as is well known in the art, that all the inputs 5a to 5g to the combinational logic blocks 2a, 2b will be connected to the output of a scan cell, even though all are not shown so connected in FIG. 2.
The multiplexors 12a, 12b and 12c are then switched, under the control of the control signal CONTROL1 on line 14, such that the inputs on line 18a, 18b and 18c of the multiplexors are connected to the respective outputs 24a, 24b and 24c of the multiplexors. The signals on the outputs 24a, 24b and 24c of the multiplexors will now be the results outputted by the combinational logic blocks 2a, 2b in response to the test bits being placed on their respective inputs. With the control signal CONTROL1 set to connect the outputs 24a, 24b and 24c to the inputs 18a, 18b and 18c the latches 16a, 16b and 16c are clocked once by the clock signal CLOCK on line 8 such that the results outputted by the combinational logic blocks 2a, 2b are latched onto the signal lines 6a, 6b and 6c respectively. The control signal CONTROL1 on line 14 is then again changed to connect the output of the multiplexors on lines 24a, 24b and 24c to their inputs on lines 20a, 20b and 20c respectively. The latches 16a, 16b and 16c are then clocked by the clock signal CLOCK such that the results latched on the outputs 6a, 6b and 6c of the latches are serially clocked out back to the controller 11 on line 9. The controller then checks to ensure that the result bits are those expected. In addition, it will be appreciated that whilst the result bits are being scanned out on the scan chain a new set of test bits can be scanned in.
It can be seen that the above technique allows the test to be carried out without the controller needing to account for the actual operation of the combinational logic circuitry 2a, 2b.
Referring now to FIG. 3, an implementation of the latch 16a of FIG. 2 is shown. The latch 16a consists of two half-latches, or transparent latches, 26a and 28a. Each half-latch consists of a respective control node (CN) 30a, 34a and a respective storage node (SN) 32a, 36a. The clock signal CLOCK on line 8 clocks the control node 34a of half-latch 28a whilst the inverse of the clock signal CLOCK, NOTCLOCK, clocks the control node 30a. It will be understood, as is well known in the art, that the clock signals CLOCK and NOTCLOCK could be non-overlapping clock signals, or alternatively circuitry in the control nodes 30a and 34a could take account of any possible overlap of the two clocks. The latches 16b and 16c of FIG. 2 similarly comprise two half-latches. It can therefore be seen that the scan cell 10a of FIG. 2 comprises two half-latches.
FIG. 4 shows the scan cell 10a of FIG. 2 redrawn with two half latches 26a, 28a rather than a single full latch 16a so as to further illustrate the fact that the scan cell can be considered to comprise two half-latches. It will be readily understood that the scan cell 10a of FIG. 4 operates in exactly the same way as the scan cell 10a of FIG. 2.
The term half-latch is used herein to denote circuitry which acts in a data transfer state to transmit a signal from its input terminal to its output terminal with the control signal in a first state and in a data holding state to store the signal on the output terminal with the control signal in the second state. A simple implementation of a half-latch is an FET transister having its source/drain channel connected between the input terminal and the output terminal and its gate connected to receive the control signal. There is sufficient capacitance inherent in the transistor to provide the storage requirement at the output terminal. However, the storage capacity can be improved by providing an extra storage transistor. Other implementations of a half-latch are known and any suitable implementation can be used in the circuit of this invention.
It should be understood from the latch presented in FIG. 3 that the latches 16a, 16b and 16c are single edge triggered latches, and more specifically are positive edge triggered latches. Referring to FIG. 3 it will be seen that when the clock signal CLOCK is low the data on the input 24a of the latch will be transferred to the intermediate node 38a of the latch because the half-latch 26a is transparent. This data on intermediate node 38a will not be transferred to the output 22a of the latch, however, because whilst the clock signal CLOCK is low the half-latch 28a is in a data retention state. However, on a rising edge (or positive edge) of the clock signal CLOCK the data on the intermediate node 38a will be transferred to the output 22a of the latch because the half-latch 28a is transparent when the clock signal is high. It can therefore be seen that the latch 10a is called a positive edge triggered latch because data on its input 24a is transferred to its output 22a as a result of the positive transition of the clock signal CLOCK. On a negative transition there is no change to the output 22a because the half latch 28a reverts to a data storage state.
Referring back to FIG. 2, it will now be apparent that during the scan test and during normal functional operation the latches 16a, 16b and 16c function as positive edge triggered latches. Provided the latches 4a, 4b and 4c of FIG. 1, which the scan cells 10a, 10b and 10c of FIG. 2 have replaced, are also only positive edge triggered latches the structure of FIG. 2 will function adequately during both normal functional operation and during scan test.
However, a problem arises if the latches 4a, 4b and 4c of FIG. 1 are double-edge triggered latches. In a double-edge triggered latch the data value on the input is transferred to the output on both negative and positive clock transitions, i.e., twice in any given clock cycle. It will be apparent that the scan cell of FIG. 4 cannot latch on negative edge clock transitions, and that if the scan cell of FIG. 4 is used to replace double edge triggered scan latches 4a, 4b and 4c of FIG. 1 during normal functional operation of the circuit data will be lost. This is apparent since if a positive edge triggered latch replaces a double edge triggered latch and the controller still operates as if the latches were double-edge triggered latches, the data in the circuit will become corrupt or lost.
Double edge triggered latches are commonly used in circuits where it is desirable to have a fast clock as well as the normal system clock. As it is also desirable to minimise clock distribution to save layout space, double edge triggered latches offer an option of providing components operating at more than one speed of operation but which require only a single clock. Such techniques also have advantages in saving power, since it is only necessary to generate one source clock signal for two speeds of operation.
It is therefore an object of the present invention to provide a scan cell which can function as either a positive edge triggered latch or a double edge triggered latch during normal functional operation of the circuitry intended to be scan tested, but to enable it to function only as a positive edge triggered latch when scan testing of a logic structure is being performed.